PCI(Peripheral Component Interconnect) Local Bus

The PCI Local Bus is a high performance bus for interconnecting chips, expansion boards, and processor/memory subsystems. It originated at Intel in the early 1990s as a standard method of interconnecting chips on a board. It was later adopted as an industry standard administered by the PCI Special Interest Group, or “PCI SIG”. Under the PCI SIG the definition of PCI was extended to define a standard expansion bus interface connector for add-in boards.
PCI Express® to PCI Bridge:
PLDA PCI Express® to PCI Bridge is a high performance, highly-configurable, silicon-proven semiconductor IP that transparently bridges a PCI Local Bus to a PCI Express® hierarchy. The bridge IP is compliant to both the PCI Express® rev. 2.0 specification and the PCI Local Bus rev. 2.3 specification.
IP Features and Deliverables

  • PCI Express® to PCI Bridge IP core in synthesizable Verilog and VHDL RTL source code
    • Compliant to the PCI Express® Specification rev. 2.0
      • Transparent forward bridge
      • PCI Express® x1, x4
    • Compliant to the PCI Local Bus Specification rev. 2.3
      • CardBus and mini PCI support in both add-on and host-bridge mode
    • Built-in PCI arbiter can control up to 7 PCI devices
    • Built in DMA
    • PCI masters can directly transfer data to/from AHB devices
    • Concurrent DMA read, DMA write, AHB-to-PCI and PCI-to-AHB transfers
    • Compliant to the AMBA Specification rev. 2.0
      • Includes AMBA AHB bridging and interface logic
      • 32-bit AHB master and slave interfaces
      • Integrated arbiter controls up to 7 devices
    • Transparent forwarding memory transactions across the bridge
    • I/O, prefetchable memory, non-prefetchable memory windows
    • VGA/ISA Enable decoding
    • Several outstanding requests and buffer queues allow for increased throughput
    • Conversion and forwarding of Type0/Type1 Configurations transactions
    • Automatic error management and logging
    • Automatic transaction ordering (PCI and PCI Express® ordering rules)
    • Interrupt/MSI forwarding