Networks on Chip(NOC)

Network-on-Chip or Network-on-a-Chip (NoC or NOC) is an approach to designing the communication subsystem between IP cores in a System-on-a-Chip (SoC). NoCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NoC applies networking theory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections. NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs.
Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call “the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology.” In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a “public transportation” sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. A NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on “application-specific NoC topology synthesis”.
Parallelism and scalability
The wires in the links of the NoC are shared by many signals. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, a NoC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Of course, the algorithms must be designed in such a way that they offer large parallelism and can hence utilize the potential of NoC.
Benefits of adopting NoCs
Traditionally, ICs have been designed with dedicated point-to-point connections, with one wire dedicated to each signal. For large designs, in particular, this has several limitations from a physical design viewpoint. The wires occupy much of the area of the chip, and in nanometer CMOS technology, interconnects dominate both performance and dynamic power dissipation, as signal propagation in wires across the chip requires multiple clock cycles. (See Rent’s rule for a discussion of wiring requirements for point-to-point connections).
NoC links can reduce the complexity of designing wires for predictable speed, power, noise, reliability, etc., thanks to their regular, well controlled structure. From a system design viewpoint, with the advent of multi-core processor systems, a network is a natural architectural choice. A NoC can provide separation between computation and communication, support modularity and IP reuse via standard interfaces, handle synchronization issues, serve as a platform for system test, and, hence, increase engineering productivity.
Courtasy Arteris
Arteris provides Network on Chip (NoC) interconnect IP to improve performance, power consumption and die size of system on chip (SoC) devices for consumer electronics, mobile, automotive and other applications.
Traditional bus and crossbar interconnect approaches create serious problems for architects, digital and physical designers, and integrators: Massive numbers of wires, increased heat and power consumption, failed timing closure, spaghetti-like routing congestion leading to increased die area, and difficulty making changes for derivatives.
Whether you are using AXI, OCP, AHB or a proprietary protocol, Arteris Network on Chip (NoC) IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan. Having the option to configure each connection’s width, and each transaction’s dynamic priority, assures meeting latency and bandwidth requirements. And with the Arteris IP configuration tool suite, design and verification can be done easily, in a matter of days or even hours.