DDR3 Controller

DDR3 SDRAM High-Performance Controller MegaCore Functions:

  • Flexible architecture
    • Industry-standard DDR3 SDRAM device and module support
    • Ability to bolt onto the ALTMEMPHY physical interface megafunction for a complete DDR3 solution
  • Feature rich
    • Optional user-controlled refresh support
    • Power-up calibrated on-chip termination (OCT)
    • Integrated error correction coding (ECC) functionality
  • Ease of use
    • SOPC Builder support
    • Optional Avalon® Memory-Mapped local interface
    • OpenCore Plus evaluation support
    • Includes MegaWizard® Plug-In Manager interface
    • Intellectual property (IP) functional simulation modules for use in Altera-supported VHDL and Verilog HDL simulators

DDR3 Controller/PHY

Product Highlights

  • Complete DDR3 solution including memory controller, DFI PHY physical interface, digital DLL, AXI/AHB bus interface
  • Patent-pending automatic Self-Configuring Logic (SCL) technology eliminates system level timing issues
  • Low read data capture latency
  • Fast turn-around time between read and write operations
  • Optimum design closure through DFI PHY macros
  • Chip/system yield improvement through SCL (DFY)
  • Embedded chip/system testability (DFT)
  • Parameterizable data bus and ECC width
  • Deep command pipeline support
  • Support for built in read-modify-write
  • Fully configurable ODT window
  • Backwards compatible with DDR2 Memory Controller

Block Diagram

 DDR3 SDRAM Controller:

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules compliant with JESD79-3, DDR3 SDRAM Standard, and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to directly deal with the DDR3 memory interface.

Block Diagram for DDR3

  • Features
  • Support for all LatticeECP3 “EA” devices
  • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
  • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
  • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
  • Supports x4, x8, and x16 device configurations
  • Support for unbuffered DDR3 DIMM and DDR3 RDIMM module
  • Supports up to one DIMM and two ranks per DIMM
  • Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
  • Programmable CAS latency
  • Programmable CAS Write Latency
  • Read burst type of nibble sequential or interleave
  • Supports automatic DDR3 SDRAM initialization and refresh
  • Automatic Write Leveling for each DQS for DIMM applications. Option to switch of write leveling for On-board memory applications.
  • Supports Power Down Mode
  • Supports Dynamic On-Die Termination (ODT) controls
  • Termination Data Strobe (TDQS) for x8 widths only
  • LatticeECP3 I/O primitives manage read skews (Read Leveling equivalent)
  • Automatic Programmable Interval Refresh or User Initiated Refresh
  • Option for controlling memory reset outside the controller