DDR2 Controller

DDR2 SDRAM Controller – Pipelined:
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR2 SDRAM. The memory controller provides a generic command interface to the user’s application. This interface reduces the effort to integrate the module with the remainder of the application and minimizes the need to deal with the DDR2 SDRAM command interface. The timing parameters for the memory can be set through the signals that are input to the core as part of the configuration interface. This enables switching between different memory devices and modification of timing parameters to suit the application using the same netlist. DDR SDRAM Controller - Pipelined Block Diagram

  • Interfaces to Industry Standard DDR2 SDRAM
  • High-Performance DDR2 533/400/333/266/200/133 operation
  • Programmable Burst Lengths of 4 or 8
  • Programmable CAS Latency of 3, 4, 5 or 6 Cycles
  • Intelligent Bank Management to Minimize ACTIVE Commands
  • Supports All Standard DDR Commands
  • Synchronous Implementation for Reliable Operation
  • Command Pipeline to Maximize Throughput
  • Up to 4 chip selects for multiple DIMM support
  • Supports all Common Memory Configurations
    • SDRAM data path widths of 8, 16, 32, 64 and 72 bits
    • Variable address widths for different memory devices
    • Programmable timing parameters
    • Byte level writing through Data Mask signals
    • Burst termination

DDR2 Controller (267 MHz and Above) Using Virtex-4 Devices:

DDR2 SDRAM devices offer new features that go beyond the DDR SDRAM specification and
enable the DDR2 device to operate at data rates of 666 Mb/s. High data rates require higher
performance from the controller and the I/Os in the FPGA. To achieve the desired bandwidth, it
is essential for the controller to operate synchronously with the operating speed of the memory.