DDR Controller

DDR SDRAM Controller Using Virtex-4 FPGA Devices:
This application note describes a DDR SDRAM controller implemented in a Virtex™-4 XC4VLX25 FF668 -10C device. This implementation uses direct clocking for data capture an an automatic calibration circuit to adjust delay on the data lines. DDR SDRAM devices are low-cost, high-density storage resources that are widely available from many memory vendors. This reference design has been developed using both SDRAM components and DIMMs.
DDR SDRAM CONTROLLER:The DDR SDRAM uses double data rate architecture to achieve high-speed data transfers. DDR SDRAM ( referred to as DDR) transfers data on both the rising and falling edge of the clock. This reference design provides an implementation of the DDR memory controller implemented in Lattice ORCA Series 4 FPGA device. This DDR controller is typically implemented in a system between the DDR and the bus master. Figure 1 shows the relationship of the controller between the bus master and the DDR. The bus master could be either a microprocessor like Intel’s i960 or a user’s proprietary module interface. For illustration purpose, the Micron’s 4M x 8 x 4Banks DDR SDRAM is chosen for this design. The design was verified using Micron SDRAM simulation model. DDR SDRAM Controller
Key Features:

  • Extreme performance, high bandwidth, and low-latency from an advanced reordering engine
  • Configurable to fit unique design characteristics
  • Silicon-proven with 260+ design wins & 100+ chips in silicon
  • Supports popular on-chip bus standards incl. AXI4, AXI, AHB, and OCP


  • Advanced and configurable architecture allows maximum performance in a wide range of different system environments
  • Popular SoC interface bus standards such as AXI4, AXI, AHB and OCP are supported. Traffic can come from a single requestor or may be arbitrated from multiple ports using a choice of different flexible arbitration algorithms in the arbitration engine
  • A command queue holds a list of upcoming commands and the ordering engine reorders commands for user-assigned priority and increased bandwidth while maintaining coherency
  • The transaction processing unit watches the command queue and does memory preparation for future commands in advance, so that commands may execute as soon as they reach the head of the queue
  • Performance and power tuning registers use parameters from Cadence SOMA files as input to get the maximum performance from each memory; performance and power can be further enhanced with a range of adjustments
  • Uses the DFI interface to the PHY, allowing the use of Cadence’s PHY, a range of available 3rd party PHYs, or the customer’s own PHY
  • Supports all the major DRAM devices: DDR1, DDR2, DDR3, DDR4, Wide-IO, LPDDR1, LPDDR2, and LPDDR2-NVM

DRAM Memory Controller Diagram