The Ittiam PCI Express Device IP is a licensable and synthesizable HDL implementation of PCIe Standards 1.1 and 2.0. This IP provides a bridge functionality between PCIe and AHB / AXI buses.

• SoC Designs
• Wireless LAN NICs
• Compliant to PCIe Standards 1.1 and 2.0
• Configurable to 1x,4x, 8x, 16x and 32x PCIe links
• User configurable buffer sizes for design optimality
• Supports Bus Mastering functionality on the PCIe interface
• Supports Slave functionality for host configuration space accesses on the PCIe interface
• Standard PIPE interface to connect to PCIe PHY analog IP / chipset.
• Versions available for  AMBA AHB specification Rev 2.0 and AMBA AXI specs Rev 1.0
• In built DMA with AHB / AXI Master (32-bit) interface
• Supports AHB/AXI slave (32-bit) interface for configuration and register access
• Supports Interrupt generation on the AHB/AXI side and the PCIe
• PCI Express Device Verilog RTL Source Code
• Verilog Test Bench Framework
• Synthesis Projects, Scripts, and Guidelines
• RTL Reference Manuals
• RTL Verification Plan, Test cases
• Sample driver C source code on AHB (ARM) side
• Altera Arria, ArriaII, Stratix III, Stratix IV, Stratix V
• Xilinx Spartan 6, Virtex 5, Virtex 6
• Altera – Quartus Flow
• Xilinx – ISE Foundation Flow
• ModelSim PE, VCS, NC-Verilog
• Synopsys DC, Cadence RTL Encounter