DDR2 SDRAM Interface for Spartan-3 Generation FPGAs:
This application note describes a DDR2 SDRAM interface implementation in a Spartan®-3 generation FPGA, interfacing with a Micron DDR2 SDRAM device. This document provides a brief overview of the DDR2 SDRAM device features, followed by a detailed explanation of the DDR2 SDRAM interface implementation.
MCU to SDRAM interface
The purpose of this project is to create a simple interface between an MCU that doesn’t support DRAM, and a standard single-rate SDRAM chip. This allows small MCUs that happen to have a large memory space, to access more storage than they normally have, without having to spend lots of money and board space on static ram.
The project consists of two parts: First, the hardware. In this case, we’re interfacing a Renesas M32C/87 16-bit MCU with a 16Mb external address space (minus some reserved areas) with an 8Mb or 16Mb Micron SDRAM chip. The interface is a Spartan 3A FPGA, which happens to come in a TQFP package for easy home soldering. The test board is a four-layer board because it vastly simplifies the power system, and I can make them at home as long as they’re not too complex. There are also two headers for my logic analyzer; one on the MCU side and one on the FPGA side. The main signals are on the top; the bottom has the header and programming signals.
This application note describes a DDR2 SDRAM interface implementation in a Spartan®-3 generation FPGA, interfacing with a Micron DDR2 SDRAM device. This document provides a brief overview of the DDR2 SDRAM device features, followed by a detailed explanation of the DDR2 SDRAM interface implementation.
MCU to SDRAM interface
The purpose of this project is to create a simple interface between an MCU that doesn’t support DRAM, and a standard single-rate SDRAM chip. This allows small MCUs that happen to have a large memory space, to access more storage than they normally have, without having to spend lots of money and board space on static ram.
The project consists of two parts: First, the hardware. In this case, we’re interfacing a Renesas M32C/87 16-bit MCU with a 16Mb external address space (minus some reserved areas) with an 8Mb or 16Mb Micron SDRAM chip. The interface is a Spartan 3A FPGA, which happens to come in a TQFP package for easy home soldering. The test board is a four-layer board because it vastly simplifies the power system, and I can make them at home as long as they’re not too complex. There are also two headers for my logic analyzer; one on the MCU side and one on the FPGA side. The main signals are on the top; the bottom has the header and programming signals.