Today’s electronic systems merge multimedia, data and signal processing, and digital communication functions on single die. Thus these systems are becoming true SoC (System-on-Chip) designs. This development is making traditional design and implementation methods limited and insufficient. Implementing an interconnect structure of a complex SoC is one of the issues which cannot be solved without new methods and solutions. In this paper a flexible structure for onchip communication between IP (Intellectual Property) blocks in gigatransistor SoCs is introduced. This approach uses communication scheme based on packet transfer and error correction. Data transfers between communicating components are implemented using high-speed serial communication lines and asynchronous block interfaces, which themselves form IP for flexible interconnect implementation.
The future SoC implementations in year 2005 and beyond will be made in technologies with minimum feature size in the range of 0.05 – 0.10 μm. The application specific integrated circuits will be up to a billion transistor systems operating at 1 GHz in very demanding self-induced noise conditions. The design is no more a block level problem, but a global communication issue. The key elements in achieving functional silicon with high operating frequency and low power consumption will be the on-chip communications and interconnects.
System-on-Chip Communication Architectures
Due to noise constraints on the large SoCs, the communication channels will not form wide buses as currently implemented on-chip and on PCBs. Thus, performance optimization will be very different and the overall communication will resemble more computer networking than traditional bus based
design. In fact, the System-on-Chip will resemble a computer network also since it will contain several processor cores with shared/distributed memory. The use of processors and configurable communications will be the key to flexibility. Reconfigurable processors and application specific processors as a part of the integration platforms can further add flexibility to the system. One of the central ideas is to implement the custom logic blocks as peripherals or (application specific or reconfigurable) processors.The system would thus ideally consist of processorbased subsystems.
The functionality is assumed to be available as IP blocks, but the communication architecture needs to be established between the blocks. Such architecture can be, e.g., a ring, a mesh, a collection of trees or point-to-point links, or any combination of these.
The realization of the communication architecture consists of interconnect IP which needs to be
represented and abstracted for the system-level design. Due to the changing characteristics of the
communication in SoC, alternate realizations ofsystem level synchronization to the subsystems is
essential. For the synchronization, the necessary condition for flexible communication architectures is
abandoning synchronization with respect to fixed global clock signal. More flexible and protocol based
synchronization and arbitration schemes must thus be developed, such as GALS (Globally Asynchronous, Locally Synchronous). The existing IP needs to be encapsulated for use in the applied communication scheme.
In order to solve the obvious design bottleneck, especially in back-end verification, the global interconnects need to be treated as similar IP blocks as processor cores or embedded memories. This will result in significant decrease of the verification and validation times as well as improve testability. As an alternative to traditional bus based on-chip communication, a switching network is a solution proposed to combat the complexities of next.
The AXI Interconnect IP (axi_interconnect) connects one or more AXI memory mapped master devices to one or more memory mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset.