CAN 2.0 (Controller Area Network)

Features • Implements the CAN 2.0B Active Specifications
• Transmits and Receives both Standard and Extended Frames
• Transmits and Receives both Data and Remote Identifiers
• Up to 1 Mb/s Programmable Bit Rate
• Hard and Soft Synchronization
• Programmable Mask and Acceptance Registers
• Avalon Bus Compliant
• Optimized for Altera’s NIOS II Embedded Processor
• SOPC Builder Ready IP
Applications • Automotive
• Construction and Agricultural Equipment
• Biomedical
• Industrial and Home Automation
• Industry
Introduction The LogiCORE™ IP Controller Area Network (CAN) product specification describes the architecture and features of the Xilinx CAN controller core and the functionality of the various registers in the design. In addition, the CAN core user interface and its customization options are described. Defining the CAN protocol is outside the scope of this document, and knowledge of the specifications described in the References section is assumed.CAN Specification 2.0B

  • Standard and Extended Data and Remote Frames

Flexible Message Buffering and Filtering

  • Configurable number of receive buffers (2 to 31)
  • One high-priority transmit buffer
  • Configurable number of lower-priority transmit buffers (0 to 16)
  • Three independent programmable internal 29 bit acceptance filters

Easy to Use and Integrate

  • Programmable data rate up to 1 Mbit/s
  • Programmable baud rate prescaler (1/2 up to 1/256)
  • Flexible programmable interrupt sources
  • 8-bit host-controller generic interface and optional AMBA-APB
  • Buffers can be implemented as Flip-Flops, or RAM


The CAN protocol was designed specifically for automotive applications but now also used in other areas such as railways, industrial automation and medical equipment.

Block Diagram

CAN Bus Controller Block Diagram

Functional Description

The CAN bus core is founded on the basic CAN principle and meets all constraints of the CAN-specification 2.0B. For buffering of received or transmitted messages, several 13-byte buffers are used. The number of buffers can be selected before synthesis. Selecting a large number of buffers disables the need for real-time reaction to CAN messages for the host processor which significantly eases software development of the system application.

The included high-priority transmit buffer can be used to transmit an important message as fast as possible, even if several lower-priority messages are pending for transmission.

The host interface contains all necessary registers for controlling and configuring the core. The host is able to read and write all registers as a conventional RAM in memory mapped mode.

The interface to the host is software-configurable. All events on the CAN data bus or in the CAN controller core are signaled using an interrupt. Every interrupt source may be individually enabled or disabled. The CAN controller core contains three software-programmable 29-bit acceptance filters that can be used to block unwanted CAN messages, which reduces the load to the host controller.

The host controller interface is connected with the memory module by an 8-bit data and a 6-bit address bus. This enables easy interfacing to many host controller types, and therefore, a quick integration with a microcontroller.