AMBA(Advance Microcontroller Bus Architecture) 2.0

The AMBA protocol is an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals. AMBA promotes design re-use by defining a common backbone for SoC modules using specifications for ACE, AXI, AHB, APB and ATB.

    • AMBA 2.0  Master
    • AMBA 2.0 Slave
    • AMBA 2.0 Arbiter
    • AMBA BRIDGE with different application example:DMA Controller,Chache Controller.

AMBA AHB Bus Components:

AMBA AHB Bus (muxes)
AMBA AHB Bus arbiter and decoder
AMBA AHB Bus slave
AMBA AHB Bus master
AMBA AHB/APB Bus bridge
AMBA AHB/AHB Bus bridge

AMBA AHB Bus RAM Controllers:

All with AMBA AHB Bus interface
SRAM Controller
SDRAM Controller
DDR Controller
Flash Controller
Compact Flash Controller
XD Controller
Combination Controllers

AMBA AHB Bus Peripherals:

All with AMBA AHB Bus interface
DMA Engine
Ethernet 10/100 MAC + DMA
Ethernet 10/100/1000 MAC + DMA
IEEE 1394a Link Layer Controller + DMA
IEEE 1394a Link Layer Controller + OHCI compatibility
IEEE 1394b Link Layer Controller + DMA
IEEE 1394b Link Layer Controller + OHCI compatibility
PCI initiator and target + DMA
PCI/CardBus initiator and target + DMA
USB 1.1 Device + DMA
USB 2.0 Device + DMA
USB 2.0 On The Go + DMA
Utopia 1/2/2+/3/3+ + DMA

AMBA AHB Bus Subsystems:

SRAM/Flash Controller AMBA AHB Bus Subsystem
SDRAM/Flash Controller AMBA AHB Bus Subsystem
SDRAM/SRAM/Flash Controller AMBA AHB Bus Subsystem
AMBA AHB Bus Subsystem- AMBA AHB Bus, arbiter, decoder, 16 master slots, 16 slave slots, AHB/APB bridge
Multilayer AMBA AHB Bus Subsystem- up to 16 AMBA AHB Bus layers
Custom Subsystems

AMBA APB Bus Peripherals:

All with AMBA APB Bus interface
Interrupt Controller
Pulse Width Modulators (PWMs)
General Purpose I/O (GPIO)
Serial Peripheral Interface (SPI)
Reset Controller
Synopsys Verification IP for AMBA 2.0 and AMBA 3 AXI

  • Compliant with the latest AMBA 3 AXI and AMBA 2.0 specification
  • Supports all AMBA 3 AXI and AMBA 2.0 data and address widths
  • AMBA 2.0 VIP Supports AMBA, AMBA-Lite and multi-layer AHB
  • Supports all protocol transfer types and response types
  • Supports constrained randomization of protocol attributes
  • Built-in support for VMM, UVM, OVM and Verilog testbenches
  • Checks for all protocol violations
  • Logs transactions and reports on protocol violations and coverage
  • Includes user-configurable message formatting
  • Leverages Synopsys Discovery™ Verification Platform technology with full support for SystemVerilog, Vera®, Verilog and VHDL verification environments
  • Includes protocol-based scenario generation

DesignWare IP for PCI Express to AMBA 2.0 AHB Bridge:

The DesignWare® IP for PCI Express® to AMBA® 2.0 AHB™ Bridge Core (PCIe®-AHB Bridge) enables designers who use the AMBA 2.0 AHB on-chip bus to easily add PCI Express external connectivity to their AMBA 2.0 AHB-based System-on-Chip devices. The high-quality PCIe-AHB Bridge is compliant to the latest PCI-SIG® and AMBA specifications and has been extensively validated with multiple HW platforms and verification suites. The silicon-proven PCIe-AHB Bridge works in conjunction with the portfolio of DesignWare Cores for PCI Express including Endpoint, Root Complex, and Dual Mode and has been successfully implemented in a wide range of applications.

  • AHB master and slave interfaces for inbound and outbound PCI Express requests
  • Supports full PCI Express configuration, I/O requests, traffic class (EP, TD, etc.) through Bridge
  • Programmable buffer sizes for AHB Master and Slave requests and response queuing
  • Independent programmable clock rates for the PCI Express core and AHB subsystem
  • Programmable maximum number of inbound and outbound read requests for AHB
  • All burst-sizes supported for both AHB Master and Slave interfaces
  • Programmable burst lengths to support 4K read/write burst over AHB Master and Slave interfaces
  • Independent maximum read request and transfer sizes between AHB and PCI Express (transfers can be split into multiple transfers)
  • Response AHB Slave request gathering from split PCI Express completions
  • Integrated address translation between the PCIe and AMBA address spaces
  • Embedded DMA

AMBA 2 AHB to USB 3.0 Device:
PLDA AMBA 2 AHB to USB 3.0 Device is a high performance, low gate count, highly configurable semiconductor IP designed to add SuperSpeed USB device connectivity to a SoC’s AMBA AHB system bus. The controller implements all of the digital layers defined by the USB 3.0 Specification and is full backward compatible with USB 2.0.

USB 3.0 Device IP Block Diagram

  • AMBA AHB to USB 3.0 Device IP core in synthezisable Verilog RTL source code
    • Includes Physical, Link, and Protocol layers
    • Includes Device Controller
    • Complies to the USB 3.0 Specification, revision 1.0
    • Full support for legacy USB 2.0
      • With PLDA USB 2.0 Core Layer
      • Or with any USB 2.0 IP through intelligent multiplexing
    • Configurable Core frequency: 125, 250, or 500Mhz
    • 32-bit AMBA 2 AHB user interface
      • Compliant to AMBA 2 AHB rev. 2.0 specification
      • Includes 2 x AHB masters and 3 x AHB slaves
      • Asynchronous clocking between Core and AHB interface
    • Configurable buffer sizes
    • USB 3.0 PIPE interface to PHY (8-,16-, or 32-bit)
    • Full Power Management support (U1,U2,U3)
      • LFPS support
    • Up to 16 IN and OUT endpoints
    • Support Isochronous and Interrupt endpoints
    • Support Bulk Stream
  • USB 3.0/2.0 Testbench as compiled simulator libraries
  • AMBA AHB to USB 3.0 Device IP simulation models